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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:24:26 03/04/2011 
-- Design Name: 
-- Module Name:    RegisterFile - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.Definitions.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RegisterFile is
    Port ( a1 			: in  std_logic_vector(2 DOWNTO 0);
           a2 			: in  std_logic_vector(2 DOWNTO 0);
           a3 			: in  std_logic_vector(2 DOWNTO 0);
           w_in 		: in  std_logic_vector (7 downto 0);
		   clk			: in std_logic;
		   reg_file_we	: in  std_logic;
           r1 			: out  data_word_type;
           r2 			: out  data_word_type);
end RegisterFile;

architecture Behavioral of RegisterFile is
type register_bank is array (0 to 7) of std_logic_vector (7 downto 0);
signal reg_file: register_bank;

begin
	process(clk,a1,a2,a3,reg_file_we)
	begin
		if rising_edge (clk) then
			if reg_file_we='0' then 				--leo
				r1 <= reg_file(conv_integer(a1));
				r2 <= reg_file (conv_integer(a2));
			else								--escribo
				reg_file(conv_integer(a3)) <= w_in;
			end if;
		end if;
	end process;
end Behavioral;
	
